How does pll synthesizer work

Currently there is no PLL available than can frequency-hop quickly enough to meet the timing requirements of the GSM protocol. In base-station applications, two separate PLL devices are used in parallel to reduce the number of wasted slots.

While the first is generating the LO for the transmitter, the second PLL is moving to the next allocated channel. By increasing the PFD frequency. Increasing the PFD frequency increases the update of the charge pump and reduces lock time.

It also allows the loop bandwidth to be widened. Loop Bandwidth. The wider the loop bandwidth, the faster the lock time. The trade-off is that a wider loop bandwidth will reduce attenuation of spurious products and increase the integrated phase noise. A phase margin of 45 degrees produces the optimum settling transient. Avoid tuning voltages nearing ground or Vp. When the tuning voltage is within a volt of the rails of the charge pump supply Vp , the charge pump begins to operate in a saturation region.

Operation in this region will degrade settling time significantly; it may also result in mismatch between jumping-up in frequency and jumping down. Operation in this saturation region can be avoided by using the maximum Vp available or using an active loop filter. Choose plastic capacitors. Some capacitors exhibit a dielectric memory effect, which can impede lock time.

This permits a higher PFD frequency than many competitive parts, without violating the above rule—enabling lower phase noise PLL design. It is possible to generate output frequencies with resolutions of s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N. Since noise at the charge pump is multiplied up to the output at a rate of 20 logN, significant improvements in phase noise are possible.

Also offering a significant advantage is the lock-time improvement made possible by fractional-N. Current base stations require 2 PLL blocks to ensure that LOs can meet the timing requirements for transmissions. Spurious levels! A fractional-N divide by The average division is correct, but the instantaneous division is incorrect. Because of this, the PFD and charge pump are constantly trying to correct for instantaneous phase errors. The heavy digital activity of the sigma-delta modulator, which provides the averaging function, creates spurious components at the output.

The digital noise, combined with inaccuracies in matching the hard-working charge pump, results in spurious levels greater than those allowable by most communications standards. Only recently have fractional-N parts, such as the ADF, made the necessary improvements in spurious performance to allow designers to consider their use in traditional integer-N markets. What PLL devices have you released recently, how do they differ, and where would I use them?

Applications are stable reference clock generators, in cases where all clocks must be synchronized with a single reference source. They consume only 7. Great news for handset designers! Ideal for WLAN equipment in the 5. It allows the user to design passive and active loop filters in many configurations, simulate VCO, PLL, and reference noise, and model spurious and settling behavior. Once a design is completed, a custom evaluation board may be ordered based on the design using an internal weblink to Avnet.

The tool is free and may be downloaded from www. Phase noise is the critical specification for many system designers. Another major advantage is the choice of eight programmable charge-pump currents; in wideband designs where the gain of the VCO changes dramatically, the programmable currents can be adjusted to ensure loop stability and bandwidth consistency across the entire band.

While chipset solutions are prominent in the headlines, particularly for GSM, the new generation of cellular phone and base stations are still likely to initially favor discrete solutions. Discrete PLL and VCO modules offer improved noise performance and isolation, and are already in high volume production at the start of the design cycle. The demand for reduced size and current consumption in handsets has driven the development of the ADI L-series of dual synthesizers on 0.

Integrated VCO and PLL modules will be a major growth in newer system designs, where board area and cost reduction of an initial design is crucial. Using this concept it is possible to use PLLs for many applications from frequency synthesizers to FM demodulators, and signal reconstitution. To develop the phase locked loop into a digital PLL frequency synthesizer, a digital divider is placed between the VCO and the phase detector to divide the VCO frequency down.

The way in which a digital divider is added to the frequency synthesizer loop can be seen in the diagram below. Programmable dividers or counters are used in many areas of electronics, including many radio frequency applications.

They take in a pulse train like that below, and give out a slower train. In a divide by two circuit only one pulse is given out for every two that are fed in and so forth.

Some are fixed, having only one division ratio. Others are programmable and digital or logic information can be fed into them to set the division ratio. When the divider is added into the circuit the phase locked loop, PLL, still tries to reduce the phase difference between the two signals entering the phase comparator.

Again when the circuit is in lock both signals entering the comparator are exactly the same in frequency. For this to be true the voltage controlled oscillator must be running at a frequency equal to the phase comparison frequency times the division ratio. It can be seen that if the division ratio is altered by one, then the voltage controlled oscillator will have to change to the next multiple of the reference frequency. This means that the step frequency of the synthesizer is equal to the frequency entering the comparator.

It can be seen from the operation of the basic digital frequency synthesizer, that the output frequency is 'n' times the phase comparison frequency, where 'n' is the division ration.

Changing the division ratio by one is the smallest frequency change that can be made. As a result it can be seen that the smallest frequency change that can be made is equal to the comparison frequency, i. In the basic format for the digital frequency synthesizer, this is equal to the reference frequency. Most synthesizers need to be able to step in much smaller increments if they are to be of any use.

Often step sizes of 10 kHz, To achieve this the comparison frequency must be reduced. This is usually accomplished by running the reference oscillator at a frequency of a MegaHertz or so, and then dividing this signal down to the required frequency using a fixed divider. In this way a low comparison frequency can be achieved.

By changing the division ratio of the divider, the output frequency of the oscillator can be changed. This makes the frequency synthesizer programmable. These digital frequency synthesizers are ideal for many applications on their own. They perform well where the differences between channels are relatively high.

Where virtual continuous tuning using steps of 1 Hz or 10Hz may be needed, this requires very high division ratios and this can degrade the phase noise performance and give rise to other issues.

To achieve the required performance, it may be necessary to combine a digital PLL synthesizer with some analogue techniques as described below. Analogue PLL synthesizer: This form of frequency synthesizer introduces a mixer into the PLL between the voltage controlled oscillator and the phase detector.

By introducing an external signal into the other terminal of the mixer, a fixed offset equal to that of the external frequency is introduced into the loop. Care is needed when designing analogue synthesizers as there can be issues with the image signal. Although phases for the phase detector are reversed, it is still necessary to ensure that only the correct mix scenario is seen by the system.

Sometimes steering voltages may be applied to the VCO to ensure the correct operation. The two types of PLL synthesizer tend to be used in different applications. Their different attributes lend them to slightly different uses and in different RF designs, although they may often be found working alongside each other in a multiloop synthesizer.

It can provide an oscillator that can provide a very stable output for use as a local oscillator in a radio, signal source in a signal generator, etc. The PLL synthesizer will give its output on frequencies separated by the step size determined by the phase comparison frequency.

This is ideal where channelised oepration is envisaged such as in broadcast radios where the different channels are separated by set amount, VHF UHF radio communications where there are distinct channels, and also mobile communications, Wi-Fi and many other uses where there are again set channels.

Where continuous tuning is needed, radios may have a selector for the tuning increment. However for very small step sizes and high frequencies this type of frequency synthesizer does have its limitations because of the enormous division ratios.

Analogue PLL synthesizer: The analogue PLL synthesizer loop tends to be used as a translation loop where the offset provided by signal that is mixed into the loop. This could be used alongside a relatively low frequency free running oscillator to enable the variable feature of variable oscillator to be translated to a much higher frequency.

This would combine the stability of the low frequency oscillator with the high frequency capability provided by the synthesizer loop.